1. Field of the Invention
The present invention relates generally to the fabrication of a semiconductor device, and more particularly to a multilayer dielectric process for forming air gaps therein for reducing permittivity of the dielectric between interconnections.
2. Description of the Related Art
Generally speaking, semiconductor devices are formed by alternating an insulating layer and a conductor in a predetermined manner over a silicon semiconductor substrate. The conductor separated by the insulating layer is electrically connected to overlying and underlying another conductors through openings (contact hole or via) in the insulating layers. Such conductors may include impurity diffusion region and metal line made of Al (aluminium), Ti (titanium), Ta (tantalum), W (tungsten), polycrystalline silicon, or a combination thereof.
Interconnection lines (or conductors) are fashioned on the semiconductor device structure and spaced by a dielectric above an underlying conductor or substrate by a dielectric thickness. Each conductor is spaced a distance from other conductors by a dielectric within the same level of conductors. Accordingly, conductor-to-conductor capacitance (i.e., coupling capacitance) is generated. As circuit density increases, spacing between conductors decreases and thus coupling capacitance therebetween increases.
Increases in coupling capacitance between conductors eventually results in an increase in RC delay, which is an important characteristic of an integrated circuit since it limits the speed (frequency) at which the circuit or circuits can operate. The shorter the RC delay, the higher the speed of the circuit or circuits. It is therefore important that RC delay should be minimized as much as possible.
The capacitance between conductors is highly dependent on the insulator, or dielectric, used to separate them. Therefore it is required to reduce the permittivity of a dielectric material between conductors. As such, it would be desirable to employ a fabrication technique in which dielectrics between conductors achieve low permittivity. The lowest possible, or ideal, dielectric constant is 1.0, which is the dielectric constant of a vacuum, whereas air has a dielectric constant of less than 1.001.
Therefore, it is desired to form a passivation layer with low permittivity while concurrently forming air gaps therein between the conductors to reduce the coupling capacitance.
The present invention was made in view of the above problem, and the present invention is directed toward providing a multilayer dielectric process for forming air gaps within the dielectric between the interconnections for a low permittivity dielectric. The present invention uses multilayer dielectric to purposely form air gaps within the dielectric. The permittivity of air within the dielectric material is less than that of the surrounding dielectric material which allows an overall decrease in permittivity between interconnections and a corresponding increase in operation speed.
The air gaps are formed by the multilayer dielectric process. More specifically, a first dielectric layer such as PE-CVD (plasma enhanced chemical vapor deposition) oxide layer using TEOS (tetraethyl orthosilicate) source is deposited on the patterned spaced metal interconnections. The PE-CVD TEOS oxide layer is deposited to provide a poor step coverage over the interconnections, i.e., deposited relatively thickly at top sides and deposited relatively thinly at bottom sides of the patterned metal interconnections. This poor step coverage of first dielectric makes it easier to form the air gaps in subsequent second dielectric and serves to increase volume of the air gaps. The second dielectric layer is deposited over the first dielectric in such controlled manner that causes air gaps within the second dielectric. The thickness of the second dielectric is large enough to cause the formation of the air gaps therein and the air gaps are completely covered by the dielectric. This second dielectric layer preferably includes a low permittivity dielectric such as a silicon oxynitride(SiON) layer. This low permittivity advantageously reduces coupling capacitance between the patterned spaced metal lines and overlying other conductors.
Briefly, in accordance with one aspect of the present invention, there is provided a method for forming air gaps in the dielectrics between the interconnections. The method includes providing at least a pair of spaced interconnects over a semiconductor topology. The semiconductor topology includes an interlayer insulating layer at a top thereof. The method further includes depositing a first dielectric layer on the spaced interconnects and over the semiconductor substrate. The first dielectric layer is deposited relatively more thickly at top sides of the interconnects than at bottom sides of the interconnects. The first dielectric layer is made of an TEOS oxide layer by a PE-CVD technique. The method further includes depositing a second dielectric layer over the first dielectric layer to cause the formation of an air gap in the second dielectric layer and between the spaced interconnects. The second dielectric layer can be made of silicon oxynitride. Alternatively, the second dielectric layer may be made of silicon nitride (SiN). The method further includes depositing a third dielectric layer on the second dielectric layer.
According to another aspect of above mentioned-method, the method further includes depositing a silicon nitride layer over the first dielectric layer, wherein the second dielectric layer is deposited thereover to cause the formation of the air gap.
In accordance with another aspect of the present invention, there is provided a method for forming air gaps in the dielectrics between the interconnects. The method includes forming first metal patterns over a semiconductor substrate. The method further includes forming an intermetal oxide layer over the first metal patterns to a thickness of about 0.8 microns. The method further includes forming second spaced apart metal patterns over the intermetal oxide layer. The second spaced apart metal patterns are separated from each other by about 0.8 microns to 0.9 microns and have a height of about 0.15 microns. The method further includes depositing a first passivation layer of an oxide on the second metal pattern to a thickness of about 0.15 microns. The first passivation layer of an oxide is deposited thickly at a top side of the second metal pattern and is deposited thinly at a bottom side of the second metal pattern. The method further includes depositing a second passivation layer of silicon oxynitride to a thickness of about 1.2 microns, causing the formation of an air gap therein between the second metal patterns. Preferably, the air gap has a size of about 0.46 microns. The method further includes depositing a third passivation layer of a polyimide to a thickness of about 10 microns over the second passivation layer of silicon oxynitride.